/*
 * Copyright (C) Hisilicon Technologies Co., Ltd. 2012-2019. All rights reserved.
 * Description: Function of mn34220_sensor_ctl.c
 * Author: ISP SW
 * Create: 2012/06/28
 */

#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <fcntl.h>
#include <unistd.h>

#include "hi_comm_video.h"
#include "hi_sns_ctrl.h"
#include "mn34220_cmos.h"
#ifdef HI_GPIO_I2C
#include "gpioi2c_ex.h"
#else
#include "hi_i2c.h"
#endif

static int g_fd[ISP_MAX_PIPE_NUM] = {[0 ...(ISP_MAX_PIPE_NUM - 1)] = -1};
#define I2C_DEV_FILE_NUM     16
#define I2C_BUF_NUM          8
int mn34220_i2c_init(VI_PIPE vi_pipe)
{
    int ret;
    char acDevFile[I2C_DEV_FILE_NUM];
    HI_U8 u8DevNum;
    ISP_SNS_COMMBUS_U *mn34220businfo = HI_NULL;
    mn34220businfo = mn34220_get_bus_Info(vi_pipe);
    if (g_fd[vi_pipe] >= 0) {
        return HI_SUCCESS;
    }

    u8DevNum = mn34220businfo->s8I2cDev;

    snprintf_s(acDevFile, sizeof(acDevFile), sizeof(acDevFile), "/dev/i2c-%u", u8DevNum);

    g_fd[vi_pipe] = open(acDevFile, O_RDWR);

    if (g_fd[vi_pipe] < 0) {
        SNS_ERR_TRACE("Open /dev/hi_i2c_drv-%u error!\n", u8DevNum);
        return HI_FAILURE;
    }

    ret = ioctl(g_fd[vi_pipe], I2C_SLAVE_FORCE, (MN34220_I2C_ADDR >> 1));
    if (ret < 0) {
        SNS_ERR_TRACE("I2C_SLAVE_FORCE error!\n");
        close(g_fd[vi_pipe]);
        g_fd[vi_pipe] = -1;
        return ret;
    }

    return HI_SUCCESS;
}

int mn34220_i2c_exit(VI_PIPE vi_pipe)
{
    if (g_fd[vi_pipe] >= 0) {
        close(g_fd[vi_pipe]);
        g_fd[vi_pipe] = -1;
        return HI_SUCCESS;
    }
    return HI_FAILURE;
}

int mn34220_read_register(VI_PIPE vi_pipe, HI_U32 addr)
{
    return HI_SUCCESS;
}

int mn34220_write_register(VI_PIPE vi_pipe, HI_U32 addr, HI_U32 data)
{
    HI_U32 idx = 0;
    HI_S32 ret;
    HI_U8 buf[I2C_BUF_NUM];

    if (g_fd[vi_pipe] < 0) {
        return HI_SUCCESS;
    }

    if (MN34220_ADDR_BYTE == 2) {  /* 2 byte */
        buf[idx] = (addr >> 8) & 0xff;  /* shift 8 */
        idx++;
        buf[idx] = addr & 0xff;
        idx++;
    } else {
        buf[idx] = addr & 0xff;
        idx++;
    }

    if (MN34220_DATA_BYTE == 2) {  /* 2 byte */
        buf[idx] = (data >> 8) & 0xff;  /* shift 8 */
        idx++;
        buf[idx] = data & 0xff;
        idx++;
    } else {
        buf[idx] = data & 0xff;
        idx++;
    }

    ret = write(g_fd[vi_pipe], buf, (MN34220_ADDR_BYTE + MN34220_DATA_BYTE));
    if (ret < 0) {
        SNS_ERR_TRACE("I2C_WRITE DATA error!\n");
        return HI_FAILURE;
    }

    return HI_SUCCESS;
}

void mn34220_standby(VI_PIPE vi_pipe)
{
    return;
}

void mn34220_restart(VI_PIPE vi_pipe)
{
    return;
}

void mn34220_wdr_init(VI_PIPE vi_pipe);
void mn34220_wdr_720p_2to1_init(VI_PIPE vi_pipe);

void mn34220_wdr_720p_3to1_init(VI_PIPE vi_pipe);
void mn34220_wdr_720p_4to1_init(VI_PIPE vi_pipe);
void mn34220_wdr_1080p_4to1_init(VI_PIPE vi_pipe);
void mn34220_wdr_1080p_3to1_init(VI_PIPE vi_pipe);
void mn34220_linear_1080p30_init(VI_PIPE vi_pipe);
void mn34220_linear_1080p60_init(VI_PIPE vi_pipe);
void mn34220_linear_720p120_init(VI_PIPE vi_pipe);
void mn34220_linear_720p30_init(VI_PIPE vi_pipe);
void mn34220_linear_VGA240_init(VI_PIPE vi_pipe);
void mn34220_wdr_1080P_2to1_init(VI_PIPE vi_pipe);

void mn34220_init(VI_PIPE vi_pipe)
{
    WDR_MODE_E       enWDRMode;
    HI_U8            u8ImgMode;
    ISP_SNS_STATE_S *mn34220 = HI_NULL;
    mn34220 = mn34220_get_ctx(vi_pipe);
    enWDRMode   = mn34220->enWDRMode;
    u8ImgMode   = mn34220->u8ImgMode;
    if (mn34220_i2c_init(vi_pipe)) {
        return;
    }
    /* When mn34220 first init, config all registers */
    if (WDR_MODE_2To1_LINE == enWDRMode) {
        if (u8ImgMode == 2) { // 2  /* SENSOR_1080P_30FPS_MODE */
            mn34220_wdr_1080P_2to1_init(vi_pipe);
        } else if (u8ImgMode == 5) { // 5 /* SENSOR_720P_30FPS_MODE */
            mn34220_wdr_720p_2to1_init(vi_pipe);
        }
        mn34220->bInit = HI_TRUE;
        return;
    }
    if (WDR_MODE_3To1_LINE == enWDRMode) {
        if (u8ImgMode == 2) { // 2  /* SENSOR_1080P_30FPS_MODE */
            mn34220_wdr_1080p_3to1_init(vi_pipe);
        } else if (u8ImgMode == 5) { // 5 /* SENSOR_720P_30FPS_MODE */
            mn34220_wdr_720p_3to1_init(vi_pipe);
        }
        mn34220->bInit = HI_TRUE;
        return;
    }
    if (WDR_MODE_4To1_LINE == enWDRMode) {
        if (u8ImgMode == 2) { // 2  /* SENSOR_1080P_30FPS_MODE */
            mn34220_wdr_1080p_4to1_init(vi_pipe);
        } else if (u8ImgMode == 5) { // 5 /* SENSOR_720P_30FPS_MODE */
            mn34220_wdr_720p_4to1_init(vi_pipe);
        }
        mn34220->bInit = HI_TRUE;
        return;
    }
    if (u8ImgMode == 1) { // 1 /* SENSOR_1080P_60FPS_MODE */
        mn34220_linear_1080p60_init(vi_pipe);
        mn34220->bInit = HI_TRUE;
        return;
    }
    if (u8ImgMode == 2) {  // 2 /* SENSOR_1080P_30FPS_MODE */
        mn34220_linear_1080p30_init(vi_pipe);
        mn34220->bInit = HI_TRUE;
        return;
    }
    if (u8ImgMode == 3) {  /* 3 */
        mn34220_linear_720p120_init(vi_pipe);
        mn34220->bInit = HI_TRUE;
        return;
    }
    if (u8ImgMode == 4) { /* 4 */
        mn34220_linear_VGA240_init(vi_pipe);
        mn34220->bInit = HI_TRUE;
        return;
    }
    if (u8ImgMode == 5) { /* 5 */
        mn34220_linear_720p30_init(vi_pipe);
        mn34220->bInit = HI_TRUE;
        return;
    }
    mn34220->bInit = HI_TRUE;
    return;
}

void mn34220_exit(VI_PIPE vi_pipe)
{
    HI_S32 ret;
    ret = mn34220_i2c_exit(vi_pipe);
    if (ret != HI_SUCCESS) {
    }
    return;
}

/* 1080P60 and 1080P50 */
void mn34220_linear_1080p60_init(VI_PIPE vi_pipe)
{
    /*  BATCH
            N112_S12_P4_FHD_V1125_H400_12b_PLL445_60fps_MCLK37_vM17e_140226_Master.txt Org.
            VCYCLE:1125 HCYCLE:550 (@MCLK) */
    HI_S32 ret = HI_SUCCESS;
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0305, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0307, 0x24);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x0112, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x0113, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x3004, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3005, 0x64);
    ret += mn34220_write_register(vi_pipe, 0x3007, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3008, 0x90);
    ret += mn34220_write_register(vi_pipe, 0x300B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3018, 0x43);
    ret += mn34220_write_register(vi_pipe, 0x3019, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x301A, 0xB9);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x53);
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0202, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x0203, 0x63);
    ret += mn34220_write_register(vi_pipe, 0x0340, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x0341, 0x65);
    ret += mn34220_write_register(vi_pipe, 0x0342, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x0343, 0x98);
    ret += mn34220_write_register(vi_pipe, 0x0346, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0347, 0x3C);
    ret += mn34220_write_register(vi_pipe, 0x034A, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x034B, 0x7F);
    ret += mn34220_write_register(vi_pipe, 0x034E, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x034F, 0x44);
    ret += mn34220_write_register(vi_pipe, 0x3036, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3039, 0x2E);
    ret += mn34220_write_register(vi_pipe, 0x3041, 0x2C);
    ret += mn34220_write_register(vi_pipe, 0x3058, 0x0F);
    ret += mn34220_write_register(vi_pipe, 0x306E, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x306F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3074, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3098, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3099, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x309A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3101, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3104, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3106, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3107, 0xC0);
    ret += mn34220_write_register(vi_pipe, 0x312B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3141, 0x40);
    ret += mn34220_write_register(vi_pipe, 0x3143, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3144, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3145, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3146, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3147, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3148, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3149, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314B, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314C, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314D, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314F, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3150, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3152, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3153, 0xE3);
    ret += mn34220_write_register(vi_pipe, 0x3155, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3157, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3159, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x315B, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x315D, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x315F, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3161, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3163, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3165, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3167, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3169, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x316B, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x316D, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x316F, 0xC6);
    ret += mn34220_write_register(vi_pipe, 0x3171, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3173, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3175, 0x80);
    ret += mn34220_write_register(vi_pipe, 0x318E, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x318F, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3196, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x31FC, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x31FE, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x323C, 0x71);
    ret += mn34220_write_register(vi_pipe, 0x323E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3243, 0xD7);
    ret += mn34220_write_register(vi_pipe, 0x3246, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3247, 0x79);
    ret += mn34220_write_register(vi_pipe, 0x3248, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3249, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x324A, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x324B, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x324C, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3253, 0xDE);
    ret += mn34220_write_register(vi_pipe, 0x3256, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x3258, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3259, 0x49);
    ret += mn34220_write_register(vi_pipe, 0x325A, 0x39);
    ret += mn34220_write_register(vi_pipe, 0x3272, 0x46);
    ret += mn34220_write_register(vi_pipe, 0x3280, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3282, 0x0E);
    ret += mn34220_write_register(vi_pipe, 0x3285, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x3288, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3289, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x330E, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3310, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3315, 0x1F);
    ret += mn34220_write_register(vi_pipe, 0x331A, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x331B, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x332C, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3339, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x336B, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x339F, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x33A2, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x33A3, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0xD3);
    ret += mn34220_write_register(vi_pipe, 0x0100, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0101, 0x00);

    printf("===panasonic mn34220 mn34220 1080P60fps linear mode init success!=====\n");

    return;
}

/* 1080P30 and 1080P25 */
void mn34220_linear_1080p30_init(VI_PIPE vi_pipe)
{
    HI_S32 ret = HI_SUCCESS;
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0305, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0307, 0x24);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x0112, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x0113, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x3004, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3005, 0x64);
    ret += mn34220_write_register(vi_pipe, 0x3007, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x3008, 0x90);
    ret += mn34220_write_register(vi_pipe, 0x300B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3018, 0x43);
    ret += mn34220_write_register(vi_pipe, 0x3019, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x301A, 0xB9);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x53);
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0202, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x0203, 0x63);
    ret += mn34220_write_register(vi_pipe, 0x0340, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x0341, 0x65);
    ret += mn34220_write_register(vi_pipe, 0x0342, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x0343, 0x98);
    ret += mn34220_write_register(vi_pipe, 0x0346, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0347, 0x3C);
    ret += mn34220_write_register(vi_pipe, 0x034A, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x034B, 0x7F);
    ret += mn34220_write_register(vi_pipe, 0x034E, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x034F, 0x44);
    ret += mn34220_write_register(vi_pipe, 0x3036, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3039, 0x2E);
    ret += mn34220_write_register(vi_pipe, 0x3041, 0x2C);
    ret += mn34220_write_register(vi_pipe, 0x3058, 0x0F);
    ret += mn34220_write_register(vi_pipe, 0x306E, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x306F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3074, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3098, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3099, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x309A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3101, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3104, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3106, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3107, 0xC0);
    ret += mn34220_write_register(vi_pipe, 0x312B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3141, 0x40);
    ret += mn34220_write_register(vi_pipe, 0x3143, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3144, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3145, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3146, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3147, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3148, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3149, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314B, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314C, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314D, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314F, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3150, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3152, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3153, 0xE3);
    ret += mn34220_write_register(vi_pipe, 0x3155, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3157, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3159, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x315B, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x315D, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x315F, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3161, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3163, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3165, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3167, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3169, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x316B, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x316D, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x316F, 0xC6);
    ret += mn34220_write_register(vi_pipe, 0x3171, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3173, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3175, 0x80);
    ret += mn34220_write_register(vi_pipe, 0x318E, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x318F, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3196, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x31FC, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x31FE, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x323C, 0x71);
    ret += mn34220_write_register(vi_pipe, 0x323E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3243, 0xD7);
    ret += mn34220_write_register(vi_pipe, 0x3246, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3247, 0x38);
    ret += mn34220_write_register(vi_pipe, 0x3248, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3249, 0xE2);
    ret += mn34220_write_register(vi_pipe, 0x324A, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x324B, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x324C, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3253, 0xDE);
    ret += mn34220_write_register(vi_pipe, 0x3256, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x3258, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3259, 0x68);
    ret += mn34220_write_register(vi_pipe, 0x325A, 0x39);
    ret += mn34220_write_register(vi_pipe, 0x3272, 0x46);
    ret += mn34220_write_register(vi_pipe, 0x3280, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3282, 0x0E);
    ret += mn34220_write_register(vi_pipe, 0x3285, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x3288, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3289, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x330E, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3310, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3315, 0x1F);
    ret += mn34220_write_register(vi_pipe, 0x331A, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x331B, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x332C, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3339, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x336B, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x339F, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x33A2, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x33A3, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0xD3);
    ret += mn34220_write_register(vi_pipe, 0x0100, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0101, 0x00);

    printf("===panasonic mn34220 mn34220 1080P30fps linear mode init success!=====\n");

    return;
}

void mn34220_linear_720p120_init(VI_PIPE vi_pipe)
{
    // BATCH
    // N018_S12_P4_HD_V750_12b_594MHz_120fps_vM17e_141112_Mst_I2C_d.txt
    // VCYCLE:750 HCYCLE:300 (@MCLK)
    HI_S32 ret = HI_SUCCESS;
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0305, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0307, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x0112, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x0113, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x3004, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3005, 0x67);
    ret += mn34220_write_register(vi_pipe, 0x3007, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3008, 0x90);
    ret += mn34220_write_register(vi_pipe, 0x300B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3018, 0x43);
    ret += mn34220_write_register(vi_pipe, 0x3019, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x301A, 0xB9);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x53);
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0202, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0203, 0xEC);
    ret += mn34220_write_register(vi_pipe, 0x0340, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0341, 0xEE);
    ret += mn34220_write_register(vi_pipe, 0x0342, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x0343, 0xA0);
    ret += mn34220_write_register(vi_pipe, 0x0346, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0347, 0xF2);
    ret += mn34220_write_register(vi_pipe, 0x034A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x034B, 0xC9);
    ret += mn34220_write_register(vi_pipe, 0x034E, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x034F, 0xD8);
    ret += mn34220_write_register(vi_pipe, 0x3036, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3039, 0x2E);
    ret += mn34220_write_register(vi_pipe, 0x3041, 0x12);
    ret += mn34220_write_register(vi_pipe, 0x3058, 0x0F);
    ret += mn34220_write_register(vi_pipe, 0x306E, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x306F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3074, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3098, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3099, 0x40);
    ret += mn34220_write_register(vi_pipe, 0x309A, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3101, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3104, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3106, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3107, 0xC0);
    ret += mn34220_write_register(vi_pipe, 0x312B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3141, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3143, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3144, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3145, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3146, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3147, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3148, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3149, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x314A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x314B, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314C, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314D, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314E, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314F, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3150, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3152, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3153, 0xE3);
    ret += mn34220_write_register(vi_pipe, 0x3155, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x3157, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3159, 0x33);
    ret += mn34220_write_register(vi_pipe, 0x315B, 0x36);
    ret += mn34220_write_register(vi_pipe, 0x315D, 0x35);
    ret += mn34220_write_register(vi_pipe, 0x315F, 0x3C);
    ret += mn34220_write_register(vi_pipe, 0x3161, 0x3F);
    ret += mn34220_write_register(vi_pipe, 0x3163, 0x3A);
    ret += mn34220_write_register(vi_pipe, 0x3165, 0x39);
    ret += mn34220_write_register(vi_pipe, 0x3167, 0x28);
    ret += mn34220_write_register(vi_pipe, 0x3169, 0x2B);
    ret += mn34220_write_register(vi_pipe, 0x316B, 0x2E);
    ret += mn34220_write_register(vi_pipe, 0x316D, 0x2D);
    ret += mn34220_write_register(vi_pipe, 0x316F, 0x22);
    ret += mn34220_write_register(vi_pipe, 0x3171, 0x22);
    ret += mn34220_write_register(vi_pipe, 0x3173, 0x61);
    ret += mn34220_write_register(vi_pipe, 0x3175, 0x80);
    ret += mn34220_write_register(vi_pipe, 0x318E, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x318F, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3196, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x31FC, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x31FE, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x323C, 0x71);
    ret += mn34220_write_register(vi_pipe, 0x323E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3243, 0x75);
    ret += mn34220_write_register(vi_pipe, 0x3246, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3247, 0xA5);
    ret += mn34220_write_register(vi_pipe, 0x3248, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3249, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x324A, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x324B, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x324C, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3253, 0x7B);
    ret += mn34220_write_register(vi_pipe, 0x3256, 0x32);
    ret += mn34220_write_register(vi_pipe, 0x3258, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3259, 0x9A);
    ret += mn34220_write_register(vi_pipe, 0x325A, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x3272, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x3280, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3282, 0x0E);
    ret += mn34220_write_register(vi_pipe, 0x3285, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x3288, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3289, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x330E, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3310, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3315, 0x1F);
    ret += mn34220_write_register(vi_pipe, 0x331A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x331B, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x332C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3339, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x336B, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x339F, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x33A2, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x33A3, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0xD3);
    ret += mn34220_write_register(vi_pipe, 0x0100, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0101, 0x00);

    printf("===panasonic mn34220 mn34220 720P120fps linear mode init success!=====\n");
}

void mn34220_linear_720p30_init(VI_PIPE vi_pipe)
{
    HI_S32 ret = HI_SUCCESS;
    ret += mn34220_write_register(vi_pipe, 0x3022, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3023, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3002, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3003, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x0304, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0305, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0306, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0307, 0x24);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x0102, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0103, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0104, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0105, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0110, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0111, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0112, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x0113, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x0120, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0121, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0300, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0301, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x0302, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0303, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3004, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3005, 0x64);
    ret += mn34220_write_register(vi_pipe, 0x3006, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3007, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x3008, 0x90);
    ret += mn34220_write_register(vi_pipe, 0x3009, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x300A, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x300B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300D, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3010, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3011, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3012, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3013, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3014, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3015, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3016, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3017, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3018, 0x43);
    ret += mn34220_write_register(vi_pipe, 0x3019, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x301A, 0x39);
    ret += mn34220_write_register(vi_pipe, 0x301B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x301C, 0x2C);
    ret += mn34220_write_register(vi_pipe, 0x301D, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x301E, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x301F, 0x1F);
    ret += mn34220_write_register(vi_pipe, 0x3020, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3021, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x53);
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0202, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0203, 0xEC);
    ret += mn34220_write_register(vi_pipe, 0x0204, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0205, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x020E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x020F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0210, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0211, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0212, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0213, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0214, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0215, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0220, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0221, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x033E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x033F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0340, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0341, 0xEE);
    ret += mn34220_write_register(vi_pipe, 0x0342, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x0343, 0xE4);
    ret += mn34220_write_register(vi_pipe, 0x0344, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0345, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0346, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0347, 0xF2);
    ret += mn34220_write_register(vi_pipe, 0x0348, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0349, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x034A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x034B, 0xC9);
    ret += mn34220_write_register(vi_pipe, 0x034C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x034D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x034E, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x034F, 0xD8);
    ret += mn34220_write_register(vi_pipe, 0x0380, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0381, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0382, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0383, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0384, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0385, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0386, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0387, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0500, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0501, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0600, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0601, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0602, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0603, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0604, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0605, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0606, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0607, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0608, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0609, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x060A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x060B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x060C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x060D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x060E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x060F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0610, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0611, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3030, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3031, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3032, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3033, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3034, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3035, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3036, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3037, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3038, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3039, 0x24);
    ret += mn34220_write_register(vi_pipe, 0x303A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x303B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x303C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x303D, 0x28);
    ret += mn34220_write_register(vi_pipe, 0x303E, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x303F, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3040, 0xC0);
    ret += mn34220_write_register(vi_pipe, 0x3041, 0x2C);
    ret += mn34220_write_register(vi_pipe, 0x3042, 0x50);
    ret += mn34220_write_register(vi_pipe, 0x3043, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3044, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3045, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3050, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3051, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3052, 0x90);
    ret += mn34220_write_register(vi_pipe, 0x3053, 0x22);
    ret += mn34220_write_register(vi_pipe, 0x3054, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3055, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3056, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3057, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3058, 0x0F);
    ret += mn34220_write_register(vi_pipe, 0x3059, 0xFE);
    ret += mn34220_write_register(vi_pipe, 0x305A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x305B, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x305C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x305D, 0x31);
    ret += mn34220_write_register(vi_pipe, 0x305E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x305F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3060, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3061, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3062, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x3063, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x3064, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3065, 0x32);
    ret += mn34220_write_register(vi_pipe, 0x3066, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3067, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3068, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3069, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x306A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x306B, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x306C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x306D, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x306E, 0x3F);
    ret += mn34220_write_register(vi_pipe, 0x306F, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3070, 0x3F);
    ret += mn34220_write_register(vi_pipe, 0x3071, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3072, 0x3F);
    ret += mn34220_write_register(vi_pipe, 0x3073, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3074, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3075, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3076, 0x42);
    ret += mn34220_write_register(vi_pipe, 0x3077, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3078, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3079, 0x13);
    ret += mn34220_write_register(vi_pipe, 0x307A, 0x12);
    ret += mn34220_write_register(vi_pipe, 0x307B, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x307C, 0x2B);
    ret += mn34220_write_register(vi_pipe, 0x307D, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x307E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x307F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3080, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3081, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3082, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3083, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3084, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3085, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3086, 0x23);
    ret += mn34220_write_register(vi_pipe, 0x3087, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3088, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x3089, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x308A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x308B, 0x0B);
    ret += mn34220_write_register(vi_pipe, 0x308C, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x308D, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x308E, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x308F, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x3090, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3091, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3092, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3093, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x3094, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3095, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3096, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3097, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3098, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3099, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x309A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x309B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x309C, 0x53);
    ret += mn34220_write_register(vi_pipe, 0x309D, 0x54);
    ret += mn34220_write_register(vi_pipe, 0x309E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x309F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3100, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3101, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3102, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3103, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3104, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3105, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3106, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3107, 0xC0);
    ret += mn34220_write_register(vi_pipe, 0x3108, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3109, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x310A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x310B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x310C, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x310D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x310E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x310F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3110, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3111, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3112, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3113, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3114, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3115, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3116, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3117, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3118, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3119, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x311A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x311B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x311C, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x311D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x311E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x311F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3120, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3121, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3122, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3123, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3124, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3125, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3126, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3127, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3128, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3129, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3130, 0x0F);
    ret += mn34220_write_register(vi_pipe, 0x3131, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3132, 0x67);
    ret += mn34220_write_register(vi_pipe, 0x3133, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3134, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3135, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3136, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3137, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3138, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3139, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x313A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x313B, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x313C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x313D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3140, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3141, 0x40);
    ret += mn34220_write_register(vi_pipe, 0x3142, 0x50);
    ret += mn34220_write_register(vi_pipe, 0x3143, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3144, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3145, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3146, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3147, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3148, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3149, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314B, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314C, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314D, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314F, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3150, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3151, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3152, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3153, 0xF1);
    ret += mn34220_write_register(vi_pipe, 0x3154, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3155, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3156, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3157, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3158, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3159, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x315A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x315B, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x315C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x315D, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x315E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x315F, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3160, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3161, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3162, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3163, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3164, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3165, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3166, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3167, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3168, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3169, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x316A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x316B, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x316C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x316D, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x316E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x316F, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3170, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3171, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3172, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3173, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3174, 0x0B);
    ret += mn34220_write_register(vi_pipe, 0x3175, 0x80);
    ret += mn34220_write_register(vi_pipe, 0x3176, 0x88);
    ret += mn34220_write_register(vi_pipe, 0x3177, 0xA0);
    ret += mn34220_write_register(vi_pipe, 0x3178, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3179, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x317A, 0xA0);
    ret += mn34220_write_register(vi_pipe, 0x317B, 0xA2);
    ret += mn34220_write_register(vi_pipe, 0x317C, 0xA0);
    ret += mn34220_write_register(vi_pipe, 0x317D, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x317E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x317F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3180, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3181, 0x82);
    ret += mn34220_write_register(vi_pipe, 0x3182, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x3183, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x3184, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3185, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3186, 0x48);
    ret += mn34220_write_register(vi_pipe, 0x3187, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3188, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3189, 0xDE);
    ret += mn34220_write_register(vi_pipe, 0x318A, 0x6B);
    ret += mn34220_write_register(vi_pipe, 0x318B, 0x0F);
    ret += mn34220_write_register(vi_pipe, 0x318C, 0x1F);
    ret += mn34220_write_register(vi_pipe, 0x318D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x318E, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x318F, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3190, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3191, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3192, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3193, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3194, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3195, 0x40);
    ret += mn34220_write_register(vi_pipe, 0x3196, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3197, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3198, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3199, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x319A, 0x0E);
    ret += mn34220_write_register(vi_pipe, 0x319B, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x319C, 0x32);
    ret += mn34220_write_register(vi_pipe, 0x319D, 0x54);
    ret += mn34220_write_register(vi_pipe, 0x319E, 0x76);
    ret += mn34220_write_register(vi_pipe, 0x319F, 0x98);
    ret += mn34220_write_register(vi_pipe, 0x31A0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31A1, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31A2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31A3, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x31A4, 0x32);
    ret += mn34220_write_register(vi_pipe, 0x31A5, 0x54);
    ret += mn34220_write_register(vi_pipe, 0x31A6, 0x86);
    ret += mn34220_write_register(vi_pipe, 0x31A7, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x31A8, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31A9, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31AA, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31AB, 0x24);
    ret += mn34220_write_register(vi_pipe, 0x31AC, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31AD, 0x89);
    ret += mn34220_write_register(vi_pipe, 0x31AE, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x31AF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B1, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B3, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B5, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B6, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B7, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B8, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B9, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31BA, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31BB, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31BC, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31BD, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31BE, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31BF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C1, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C3, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C5, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C6, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C7, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C8, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C9, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31CA, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31CB, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31CC, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31CD, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31CE, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31CF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D1, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D3, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D5, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D6, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D7, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D8, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D9, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31DA, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31DB, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31DC, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31DD, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31DE, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31DF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E1, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E3, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E5, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E6, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E7, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E8, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E9, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31EA, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31EB, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31EC, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31ED, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31EE, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31EF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F1, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F3, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F5, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F6, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F7, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x31F8, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x31F9, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x31FA, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x31FB, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x31FC, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x31FD, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x31FE, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x31FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3200, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3201, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3202, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3203, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3204, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3205, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3206, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3207, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3208, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3209, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x320A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x320B, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x320C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x320D, 0x1A);
    ret += mn34220_write_register(vi_pipe, 0x320E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x320F, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x3210, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3211, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x3212, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3213, 0x0B);
    ret += mn34220_write_register(vi_pipe, 0x3214, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3215, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3216, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3217, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3218, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3219, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x321A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x321B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x321C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x321D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x321E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x321F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3220, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3221, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3222, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3223, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3224, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3225, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3226, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3227, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3228, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3229, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x322A, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x322B, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x322C, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x322D, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x322E, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x322F, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3230, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3231, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3232, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3233, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3234, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3235, 0xBA);
    ret += mn34220_write_register(vi_pipe, 0x3236, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3237, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3238, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3239, 0xBA);
    ret += mn34220_write_register(vi_pipe, 0x323A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x323B, 0x81);
    ret += mn34220_write_register(vi_pipe, 0x323C, 0x71);
    ret += mn34220_write_register(vi_pipe, 0x323D, 0x80);
    ret += mn34220_write_register(vi_pipe, 0x323E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x323F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3240, 0x15);
    ret += mn34220_write_register(vi_pipe, 0x3241, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x3242, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3243, 0xD7);
    ret += mn34220_write_register(vi_pipe, 0x3244, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3245, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x3246, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3247, 0x71);
    ret += mn34220_write_register(vi_pipe, 0x3248, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3249, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x324A, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x324B, 0x34);
    ret += mn34220_write_register(vi_pipe, 0x324C, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x324D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x324E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x324F, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x3250, 0x31);
    ret += mn34220_write_register(vi_pipe, 0x3251, 0x0E);
    ret += mn34220_write_register(vi_pipe, 0x3252, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3253, 0xDE);
    ret += mn34220_write_register(vi_pipe, 0x3254, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3255, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3256, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x3257, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3258, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3259, 0x41);
    ret += mn34220_write_register(vi_pipe, 0x325A, 0x39);
    ret += mn34220_write_register(vi_pipe, 0x325B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x325C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x325D, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x325E, 0x84);
    ret += mn34220_write_register(vi_pipe, 0x325F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3260, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3261, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3270, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3271, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3272, 0x46);
    ret += mn34220_write_register(vi_pipe, 0x3273, 0xAB);
    ret += mn34220_write_register(vi_pipe, 0x3274, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3275, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x3280, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3281, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3282, 0x0E);
    ret += mn34220_write_register(vi_pipe, 0x3283, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3284, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3285, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x3286, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x3287, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3288, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3289, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x328A, 0xE8);
    ret += mn34220_write_register(vi_pipe, 0x328B, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x328C, 0x75);
    ret += mn34220_write_register(vi_pipe, 0x328D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3300, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3301, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3302, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3303, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x3304, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3305, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x3306, 0x19);
    ret += mn34220_write_register(vi_pipe, 0x3307, 0x19);
    ret += mn34220_write_register(vi_pipe, 0x3308, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3309, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x330A, 0x1E);
    ret += mn34220_write_register(vi_pipe, 0x330B, 0x1E);
    ret += mn34220_write_register(vi_pipe, 0x330C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x330D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x330E, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x330F, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x3310, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3311, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3312, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3313, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3314, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3315, 0x19);
    ret += mn34220_write_register(vi_pipe, 0x3316, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x3317, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3318, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3319, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x331A, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x331B, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x331C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x331D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x331E, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x331F, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3320, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3321, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3322, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3323, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3324, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3325, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3326, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x3327, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3328, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3329, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x332A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x332B, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x332C, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x332D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x332E, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x332F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3330, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3331, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3332, 0x12);
    ret += mn34220_write_register(vi_pipe, 0x3333, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3334, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3335, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3336, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3337, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3338, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3339, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x333A, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x333B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x333C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x333D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x333E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x333F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3340, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3341, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3342, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3343, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3344, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3345, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3346, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3347, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3348, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x3349, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x334A, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x334B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x334C, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x334D, 0x1C);
    ret += mn34220_write_register(vi_pipe, 0x334E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x334F, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3350, 0x0E);
    ret += mn34220_write_register(vi_pipe, 0x3351, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3352, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3353, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3354, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3355, 0x19);
    ret += mn34220_write_register(vi_pipe, 0x3356, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3357, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3358, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x3359, 0x0B);
    ret += mn34220_write_register(vi_pipe, 0x335A, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x335B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x335C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x335D, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x335E, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x335F, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3360, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x3361, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x3362, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x3363, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3364, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3365, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3366, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x3367, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3368, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x3369, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x336A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x336B, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x336C, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x336D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x336E, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x336F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3370, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3371, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3372, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3373, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3374, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3375, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3376, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3377, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3378, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3379, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x337A, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x337B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x337C, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x337D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x337E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x337F, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3380, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3381, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3382, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3383, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3384, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x3385, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3386, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3387, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3388, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x3389, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x338A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x338B, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x338C, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x338D, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x338E, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x338F, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x3390, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3391, 0x0F);
    ret += mn34220_write_register(vi_pipe, 0x3392, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3393, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x3394, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3395, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x3396, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x3397, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x3398, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3399, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x339A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x339B, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x339C, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x339D, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x339E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x339F, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x33A0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33A1, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x33A2, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x33A3, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x33A4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33A5, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x33A6, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x33A7, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33A8, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33A9, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33AA, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33AB, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33AC, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x33AD, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x33AE, 0x3F);
    ret += mn34220_write_register(vi_pipe, 0x33AF, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x33B0, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x33B1, 0x1A);
    ret += mn34220_write_register(vi_pipe, 0x33B2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33B3, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33B4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33B5, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0xD3);
    ret += mn34220_write_register(vi_pipe, 0x0100, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0101, 0x00);

    printf("===panasonic mn34220 mn34220 720P30fps linear mode init success!=====\n");
}

void mn34220_linear_VGA240_init(VI_PIPE vi_pipe)
{
    /* #BATCH
    # N570_S12_P6_VGA_V562_10b_594MHz_240fps_vM17e_141201_Mst_I2C_d.txt
    # VCYCLE:562 HCYCLE:200 (@MCLK)
    */
    HI_S32 ret = HI_SUCCESS;
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0305, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0307, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x0112, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x0113, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x3004, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3005, 0x67);
    ret += mn34220_write_register(vi_pipe, 0x3007, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3008, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3018, 0x43);
    ret += mn34220_write_register(vi_pipe, 0x3019, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x301A, 0xB9);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x53);
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0202, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0203, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x0340, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0341, 0x32);
    ret += mn34220_write_register(vi_pipe, 0x0342, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x0343, 0x98);
    ret += mn34220_write_register(vi_pipe, 0x0346, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0347, 0x68);
    ret += mn34220_write_register(vi_pipe, 0x034A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x034B, 0x53);
    ret += mn34220_write_register(vi_pipe, 0x034E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x034F, 0xEC);
    ret += mn34220_write_register(vi_pipe, 0x3036, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3039, 0x2E);
    ret += mn34220_write_register(vi_pipe, 0x3041, 0x12);
    ret += mn34220_write_register(vi_pipe, 0x3058, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x306E, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x306F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3074, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3098, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3099, 0x40);
    ret += mn34220_write_register(vi_pipe, 0x309A, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3101, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3104, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3106, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3107, 0x40);
    ret += mn34220_write_register(vi_pipe, 0x312B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3141, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3143, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3144, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3145, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3146, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3147, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3148, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3149, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x314A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x314B, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314C, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314D, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314E, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314F, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3150, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3152, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3153, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x3155, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x3157, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3159, 0x33);
    ret += mn34220_write_register(vi_pipe, 0x315B, 0x36);
    ret += mn34220_write_register(vi_pipe, 0x315D, 0x35);
    ret += mn34220_write_register(vi_pipe, 0x315F, 0x3C);
    ret += mn34220_write_register(vi_pipe, 0x3161, 0x3F);
    ret += mn34220_write_register(vi_pipe, 0x3163, 0x3A);
    ret += mn34220_write_register(vi_pipe, 0x3165, 0x39);
    ret += mn34220_write_register(vi_pipe, 0x3167, 0x28);
    ret += mn34220_write_register(vi_pipe, 0x3169, 0x2B);
    ret += mn34220_write_register(vi_pipe, 0x316B, 0x2E);
    ret += mn34220_write_register(vi_pipe, 0x316D, 0x2D);
    ret += mn34220_write_register(vi_pipe, 0x316F, 0x22);
    ret += mn34220_write_register(vi_pipe, 0x3171, 0x22);
    ret += mn34220_write_register(vi_pipe, 0x3173, 0x61);
    ret += mn34220_write_register(vi_pipe, 0x3175, 0x80);
    ret += mn34220_write_register(vi_pipe, 0x318E, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x318F, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3196, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x31FC, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x31FE, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x323C, 0x71);
    ret += mn34220_write_register(vi_pipe, 0x323E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3243, 0x75);
    ret += mn34220_write_register(vi_pipe, 0x3246, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3247, 0xC9);
    ret += mn34220_write_register(vi_pipe, 0x3248, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3249, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x324A, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x324B, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x324C, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3253, 0x7B);
    ret += mn34220_write_register(vi_pipe, 0x3256, 0x32);
    ret += mn34220_write_register(vi_pipe, 0x3258, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3259, 0x5C);
    ret += mn34220_write_register(vi_pipe, 0x325A, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x3272, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x3280, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3282, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x3285, 0x19);
    ret += mn34220_write_register(vi_pipe, 0x3288, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3289, 0x40);
    ret += mn34220_write_register(vi_pipe, 0x330E, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3310, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3315, 0x1F);
    ret += mn34220_write_register(vi_pipe, 0x331A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x331B, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x332C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3339, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x336B, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x339F, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x33A2, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x33A3, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0xD3);
    ret += mn34220_write_register(vi_pipe, 0x0100, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0101, 0x00);

    printf("===panasonic mn34220 mn34220 VGA 240fps linear mode init success!=====\n");
}

void mn34220_wdr_init(VI_PIPE vi_pipe)
{
    /* # N035_S12_P2x2_FHD_WDRx2_V1250_H360_12b_30fps_MCLK37_vE13_140401_Master.txt */
    /* # VCYCLE:1250 HCYCLE:990 (@MCLK) */
    /* for ES version */
    HI_S32 ret = HI_SUCCESS;
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0305, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0307, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x0112, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x0113, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x3004, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3005, 0x67);
    ret += mn34220_write_register(vi_pipe, 0x3007, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3008, 0x90);
    ret += mn34220_write_register(vi_pipe, 0x300B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3018, 0x43);
    ret += mn34220_write_register(vi_pipe, 0x3019, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x301A, 0xB9);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x53);
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0202, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0203, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x0340, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x0341, 0xE2);
    ret += mn34220_write_register(vi_pipe, 0x0342, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x0343, 0xA0);
    ret += mn34220_write_register(vi_pipe, 0x0346, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0347, 0x3C);
    ret += mn34220_write_register(vi_pipe, 0x034A, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x034B, 0x7F);
    ret += mn34220_write_register(vi_pipe, 0x034E, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x034F, 0x44);
    ret += mn34220_write_register(vi_pipe, 0x3036, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3039, 0x2E);
    ret += mn34220_write_register(vi_pipe, 0x3041, 0x2C);
    ret += mn34220_write_register(vi_pipe, 0x3058, 0x0F);
    ret += mn34220_write_register(vi_pipe, 0x306E, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x306F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3074, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3098, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3099, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x309A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3101, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3104, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3106, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3107, 0xC0);
    ret += mn34220_write_register(vi_pipe, 0x312B, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x312D, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x312F, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x3141, 0x40);
    ret += mn34220_write_register(vi_pipe, 0x3143, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3144, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3145, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3146, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3147, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3148, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3149, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314A, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x314B, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x314C, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x314D, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x314E, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x314F, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3150, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x3152, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3153, 0xE3);
    ret += mn34220_write_register(vi_pipe, 0x3155, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3157, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3159, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x315B, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x315D, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x315F, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3161, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3163, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3165, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3167, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3169, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x316B, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x316D, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x316F, 0xC6);
    ret += mn34220_write_register(vi_pipe, 0x3171, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3173, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3175, 0x80);
    ret += mn34220_write_register(vi_pipe, 0x318E, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x318F, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3196, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x31FC, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x31FE, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x323C, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x323E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3243, 0xD1);
    ret += mn34220_write_register(vi_pipe, 0x3246, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3247, 0xD6);
    ret += mn34220_write_register(vi_pipe, 0x3248, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3249, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x324A, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x324B, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x324C, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3253, 0xD4);
    ret += mn34220_write_register(vi_pipe, 0x3256, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x3258, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3259, 0xE6);
    ret += mn34220_write_register(vi_pipe, 0x325A, 0x39);
    ret += mn34220_write_register(vi_pipe, 0x3272, 0x55);
    ret += mn34220_write_register(vi_pipe, 0x3280, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3282, 0x0E);
    ret += mn34220_write_register(vi_pipe, 0x3285, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x3288, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3289, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x330E, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3310, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3315, 0x1F);
    ret += mn34220_write_register(vi_pipe, 0x331A, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x331B, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x332C, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3339, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x336B, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x339F, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x33A2, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x33A3, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0xD3);
    ret += mn34220_write_register(vi_pipe, 0x0100, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0101, 0x00);

    printf("===panasonic mn34220 mn34220 1080P30fps 2to1 WDR(60fps->30fps) init success!=====\n");

    return;
}

void mn34220_wdr_720p_2to1_init(VI_PIPE vi_pipe)
{
    HI_S32 ret = HI_SUCCESS;
    ret += mn34220_write_register(vi_pipe, 0x3022, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3023, 0x33);
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3002, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3003, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x0304, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0305, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0306, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0307, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x0102, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0103, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0104, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0105, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0110, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0111, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0112, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x0113, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x0120, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0121, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0300, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0301, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x0302, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0303, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3004, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3005, 0x67);
    ret += mn34220_write_register(vi_pipe, 0x3006, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3007, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x3008, 0x90);    // 2ch 2port
    ret += mn34220_write_register(vi_pipe, 0x3009, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x300A, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x300B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300D, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3010, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3011, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3012, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3013, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3014, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3015, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3016, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3017, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3018, 0x43);
    ret += mn34220_write_register(vi_pipe, 0x3019, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x301A, 0xB9);
    ret += mn34220_write_register(vi_pipe, 0x301B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x301C, 0x2B);
    ret += mn34220_write_register(vi_pipe, 0x301D, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x301E, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x301F, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3020, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3021, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x53);
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0202, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0203, 0xEC);
    ret += mn34220_write_register(vi_pipe, 0x0204, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0205, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x020E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x020F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0210, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0211, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0212, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0213, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0214, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0215, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0220, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0221, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x033E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x033F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0340, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0341, 0xEE);
    ret += mn34220_write_register(vi_pipe, 0x0342, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x0343, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x0344, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0345, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0346, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0347, 0xF2);
    ret += mn34220_write_register(vi_pipe, 0x0348, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0349, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x034A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x034B, 0xC9);
    ret += mn34220_write_register(vi_pipe, 0x034C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x034D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x034E, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x034F, 0xD8);
    ret += mn34220_write_register(vi_pipe, 0x0380, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0381, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0382, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0383, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0384, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0385, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0386, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0387, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0500, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0501, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0600, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0601, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0602, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0603, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0604, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0605, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0606, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0607, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0608, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0609, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x060A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x060B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x060C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x060D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x060E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x060F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0610, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0611, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3030, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3031, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3032, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3033, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3034, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3035, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3036, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3037, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3038, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3039, 0x2E);
    ret += mn34220_write_register(vi_pipe, 0x303A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x303B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x303C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x303D, 0x28);
    ret += mn34220_write_register(vi_pipe, 0x303E, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x303F, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3040, 0xC0);
    ret += mn34220_write_register(vi_pipe, 0x3041, 0x12);
    ret += mn34220_write_register(vi_pipe, 0x3042, 0x50);
    ret += mn34220_write_register(vi_pipe, 0x3043, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3044, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3045, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3050, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3051, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3052, 0x90);
    ret += mn34220_write_register(vi_pipe, 0x3053, 0x22);
    ret += mn34220_write_register(vi_pipe, 0x3054, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3055, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3056, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3057, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3058, 0x0F);
    ret += mn34220_write_register(vi_pipe, 0x3059, 0xFE);
    ret += mn34220_write_register(vi_pipe, 0x305A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x305B, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x305C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x305D, 0x31);
    ret += mn34220_write_register(vi_pipe, 0x305E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x305F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3060, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3061, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3062, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x3063, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x3064, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3065, 0x32);
    ret += mn34220_write_register(vi_pipe, 0x3066, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3067, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3068, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3069, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x306A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x306B, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x306C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x306D, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x306E, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x306F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3070, 0x3F);
    ret += mn34220_write_register(vi_pipe, 0x3071, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3072, 0x3F);
    ret += mn34220_write_register(vi_pipe, 0x3073, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3074, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3075, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3076, 0x42);
    ret += mn34220_write_register(vi_pipe, 0x3077, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3078, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3079, 0x13);
    ret += mn34220_write_register(vi_pipe, 0x307A, 0x12);
    ret += mn34220_write_register(vi_pipe, 0x307B, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x307C, 0x2B);
    ret += mn34220_write_register(vi_pipe, 0x307D, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x307E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x307F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3080, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3081, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3082, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3083, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3084, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3085, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3086, 0x23);
    ret += mn34220_write_register(vi_pipe, 0x3087, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3088, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x3089, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x308A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x308B, 0x0B);
    ret += mn34220_write_register(vi_pipe, 0x308C, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x308D, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x308E, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x308F, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x3090, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3091, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3092, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3093, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x3094, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3095, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3096, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3097, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3098, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3099, 0x40);
    ret += mn34220_write_register(vi_pipe, 0x309A, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x309B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x309C, 0x53);
    ret += mn34220_write_register(vi_pipe, 0x309D, 0x54);
    ret += mn34220_write_register(vi_pipe, 0x309E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x309F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3100, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3101, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3102, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3103, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3104, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3105, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3106, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3107, 0xC0);
    ret += mn34220_write_register(vi_pipe, 0x3108, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3109, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x310A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x310B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x310C, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x310D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x310E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x310F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3110, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3111, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3112, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3113, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3114, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3115, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3116, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3117, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3118, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3119, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x311A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x311B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x311C, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x311D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x311E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x311F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3120, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3121, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3122, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3123, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3124, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3125, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3126, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3127, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3128, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3129, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312B, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x312C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312D, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x312E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312F, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x3130, 0x0F);
    ret += mn34220_write_register(vi_pipe, 0x3131, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3132, 0x67);
    ret += mn34220_write_register(vi_pipe, 0x3133, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3134, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3135, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3136, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3137, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3138, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3139, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x313A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x313B, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x313C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x313D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3140, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3141, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3142, 0x50);
    ret += mn34220_write_register(vi_pipe, 0x3143, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3144, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3145, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3146, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3147, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3148, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3149, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x314A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x314B, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314C, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314D, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314E, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314F, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3150, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3151, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3152, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3153, 0xE3);
    ret += mn34220_write_register(vi_pipe, 0x3154, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3155, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x3156, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3157, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3158, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3159, 0x33);
    ret += mn34220_write_register(vi_pipe, 0x315A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x315B, 0x36);
    ret += mn34220_write_register(vi_pipe, 0x315C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x315D, 0x35);
    ret += mn34220_write_register(vi_pipe, 0x315E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x315F, 0x3C);
    ret += mn34220_write_register(vi_pipe, 0x3160, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3161, 0x3F);
    ret += mn34220_write_register(vi_pipe, 0x3162, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3163, 0x3A);
    ret += mn34220_write_register(vi_pipe, 0x3164, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3165, 0x39);
    ret += mn34220_write_register(vi_pipe, 0x3166, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3167, 0x28);
    ret += mn34220_write_register(vi_pipe, 0x3168, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3169, 0x2B);
    ret += mn34220_write_register(vi_pipe, 0x316A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x316B, 0x2E);
    ret += mn34220_write_register(vi_pipe, 0x316C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x316D, 0x2D);
    ret += mn34220_write_register(vi_pipe, 0x316E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x316F, 0x22);
    ret += mn34220_write_register(vi_pipe, 0x3170, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3171, 0x22);
    ret += mn34220_write_register(vi_pipe, 0x3172, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3173, 0x61);
    ret += mn34220_write_register(vi_pipe, 0x3174, 0x0B);
    ret += mn34220_write_register(vi_pipe, 0x3175, 0x80);
    ret += mn34220_write_register(vi_pipe, 0x3176, 0x88);
    ret += mn34220_write_register(vi_pipe, 0x3177, 0xA0);
    ret += mn34220_write_register(vi_pipe, 0x3178, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3179, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x317A, 0xA0);
    ret += mn34220_write_register(vi_pipe, 0x317B, 0xA2);
    ret += mn34220_write_register(vi_pipe, 0x317C, 0xA0);
    ret += mn34220_write_register(vi_pipe, 0x317D, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x317E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x317F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3180, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3181, 0x82);
    ret += mn34220_write_register(vi_pipe, 0x3182, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x3183, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x3184, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3185, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3186, 0x48);
    ret += mn34220_write_register(vi_pipe, 0x3187, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3188, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3189, 0xDE);
    ret += mn34220_write_register(vi_pipe, 0x318A, 0x6B);
    ret += mn34220_write_register(vi_pipe, 0x318B, 0x0F);
    ret += mn34220_write_register(vi_pipe, 0x318C, 0x1F);
    ret += mn34220_write_register(vi_pipe, 0x318D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x318E, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x318F, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3190, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3191, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3192, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3193, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3194, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3195, 0x40);
    ret += mn34220_write_register(vi_pipe, 0x3196, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3197, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3198, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3199, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x319A, 0x0E);
    ret += mn34220_write_register(vi_pipe, 0x319B, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x319C, 0x32);
    ret += mn34220_write_register(vi_pipe, 0x319D, 0x54);
    ret += mn34220_write_register(vi_pipe, 0x319E, 0x76);
    ret += mn34220_write_register(vi_pipe, 0x319F, 0x98);
    ret += mn34220_write_register(vi_pipe, 0x31A0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31A1, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31A2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31A3, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x31A4, 0x32);
    ret += mn34220_write_register(vi_pipe, 0x31A5, 0x54);
    ret += mn34220_write_register(vi_pipe, 0x31A6, 0x86);
    ret += mn34220_write_register(vi_pipe, 0x31A7, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x31A8, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31A9, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31AA, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31AB, 0x24);
    ret += mn34220_write_register(vi_pipe, 0x31AC, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31AD, 0x89);
    ret += mn34220_write_register(vi_pipe, 0x31AE, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x31AF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B1, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B3, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B5, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B6, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B7, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B8, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B9, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31BA, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31BB, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31BC, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31BD, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31BE, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31BF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C1, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C3, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C5, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C6, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C7, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C8, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C9, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31CA, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31CB, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31CC, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31CD, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31CE, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31CF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D1, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D3, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D5, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D6, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D7, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D8, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D9, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31DA, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31DB, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31DC, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31DD, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31DE, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31DF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E1, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E3, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E5, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E6, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E7, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E8, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E9, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31EA, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31EB, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31EC, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31ED, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31EE, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31EF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F1, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F3, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F5, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F6, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F7, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x31F8, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x31F9, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x31FA, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x31FB, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x31FC, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x31FD, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x31FE, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x31FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3200, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3201, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3202, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3203, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3204, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3205, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3206, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3207, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3208, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3209, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x320A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x320B, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x320C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x320D, 0x1A);
    ret += mn34220_write_register(vi_pipe, 0x320E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x320F, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x3210, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3211, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x3212, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3213, 0x0B);
    ret += mn34220_write_register(vi_pipe, 0x3214, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3215, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3216, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3217, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3218, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3219, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x321A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x321B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x321C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x321D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x321E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x321F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3220, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3221, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3222, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3223, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3224, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3225, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3226, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3227, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3228, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3229, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x322A, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x322B, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x322C, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x322D, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x322E, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x322F, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3230, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3231, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3232, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3233, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3234, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3235, 0xBA);
    ret += mn34220_write_register(vi_pipe, 0x3236, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3237, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3238, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3239, 0xBA);
    ret += mn34220_write_register(vi_pipe, 0x323A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x323B, 0x81);
    ret += mn34220_write_register(vi_pipe, 0x323C, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x323D, 0x80);
    ret += mn34220_write_register(vi_pipe, 0x323E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x323F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3240, 0x15);
    ret += mn34220_write_register(vi_pipe, 0x3241, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x3242, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3243, 0x75);
    ret += mn34220_write_register(vi_pipe, 0x3244, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3245, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x3246, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3247, 0x3B);
    ret += mn34220_write_register(vi_pipe, 0x3248, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3249, 0xAB);
    ret += mn34220_write_register(vi_pipe, 0x324A, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x324B, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x324C, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x324D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x324E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x324F, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x3250, 0x31);
    ret += mn34220_write_register(vi_pipe, 0x3251, 0x0E);
    ret += mn34220_write_register(vi_pipe, 0x3252, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3253, 0x7B);
    ret += mn34220_write_register(vi_pipe, 0x3254, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3255, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3256, 0x32);
    ret += mn34220_write_register(vi_pipe, 0x3257, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3258, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3259, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x325A, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x325B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x325C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x325D, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x325E, 0x84);
    ret += mn34220_write_register(vi_pipe, 0x325F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3260, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3261, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3270, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3271, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3272, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x3273, 0xAB);
    ret += mn34220_write_register(vi_pipe, 0x3274, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3275, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x3280, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3281, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3282, 0x0E);
    ret += mn34220_write_register(vi_pipe, 0x3283, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3284, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3285, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x3286, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x3287, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3288, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3289, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x328A, 0xE8);
    ret += mn34220_write_register(vi_pipe, 0x328B, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x328C, 0x75);
    ret += mn34220_write_register(vi_pipe, 0x328D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3300, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3301, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3302, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3303, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x3304, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3305, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x3306, 0x19);
    ret += mn34220_write_register(vi_pipe, 0x3307, 0x19);
    ret += mn34220_write_register(vi_pipe, 0x3308, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3309, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x330A, 0x1E);
    ret += mn34220_write_register(vi_pipe, 0x330B, 0x1E);
    ret += mn34220_write_register(vi_pipe, 0x330C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x330D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x330E, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x330F, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x3310, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3311, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3312, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3313, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3314, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3315, 0x1F);
    ret += mn34220_write_register(vi_pipe, 0x3316, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x3317, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3318, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3319, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x331A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x331B, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x331C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x331D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x331E, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x331F, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3320, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3321, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3322, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3323, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3324, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3325, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3326, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x3327, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3328, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3329, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x332A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x332B, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x332C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x332D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x332E, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x332F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3330, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3331, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3332, 0x12);
    ret += mn34220_write_register(vi_pipe, 0x3333, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3334, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3335, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3336, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3337, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3338, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3339, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x333A, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x333B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x333C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x333D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x333E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x333F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3340, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3341, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3342, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3343, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3344, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3345, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3346, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3347, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3348, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x3349, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x334A, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x334B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x334C, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x334D, 0x1C);
    ret += mn34220_write_register(vi_pipe, 0x334E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x334F, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3350, 0x0E);
    ret += mn34220_write_register(vi_pipe, 0x3351, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3352, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3353, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3354, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3355, 0x19);
    ret += mn34220_write_register(vi_pipe, 0x3356, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3357, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3358, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x3359, 0x0B);
    ret += mn34220_write_register(vi_pipe, 0x335A, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x335B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x335C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x335D, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x335E, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x335F, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3360, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x3361, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x3362, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x3363, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3364, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3365, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3366, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x3367, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3368, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x3369, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x336A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x336B, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x336C, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x336D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x336E, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x336F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3370, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3371, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3372, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3373, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3374, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3375, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3376, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3377, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3378, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3379, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x337A, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x337B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x337C, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x337D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x337E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x337F, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3380, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3381, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3382, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3383, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3384, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x3385, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3386, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3387, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3388, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x3389, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x338A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x338B, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x338C, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x338D, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x338E, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x338F, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x3390, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3391, 0x0F);
    ret += mn34220_write_register(vi_pipe, 0x3392, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3393, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x3394, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3395, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x3396, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x3397, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x3398, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3399, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x339A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x339B, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x339C, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x339D, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x339E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x339F, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x33A0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33A1, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x33A2, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x33A3, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x33A4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33A5, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x33A6, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x33A7, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33A8, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33A9, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33AA, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33AB, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33AC, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x33AD, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x33AE, 0x3F);
    ret += mn34220_write_register(vi_pipe, 0x33AF, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x33B0, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x33B1, 0x1A);
    ret += mn34220_write_register(vi_pipe, 0x33B2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33B3, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33B4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33B5, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0xD3);
    ret += mn34220_write_register(vi_pipe, 0x0100, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0101, 0x00);
}

void mn34220_wdr_720p_3to1_init(VI_PIPE vi_pipe)
{
    /* # NK20_S12_P2x2_HD_i2c_write 0 0x6cDRx3_V750_12b_297MHz_20fps_vM17e_150626_MCLK37_Mst_I2C_d.txt */
    /* # VCYCLE:750 HCYCLE:2475 (@MCLK) */
    HI_S32 ret = HI_SUCCESS;
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0305, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0307, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x0112, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x0113, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x3007, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x3008, 0x90);
    ret += mn34220_write_register(vi_pipe, 0x300B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3018, 0x43);
    ret += mn34220_write_register(vi_pipe, 0x3019, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x301A, 0xB9);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x53);
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0203, 0xEC);
    ret += mn34220_write_register(vi_pipe, 0x0340, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0341, 0xEE);
    ret += mn34220_write_register(vi_pipe, 0x0342, 0x19);
    ret += mn34220_write_register(vi_pipe, 0x0343, 0xC8);
    ret += mn34220_write_register(vi_pipe, 0x0347, 0xF2);
    ret += mn34220_write_register(vi_pipe, 0x034A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x034B, 0xC9);
    ret += mn34220_write_register(vi_pipe, 0x034E, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x034F, 0xD8);
    ret += mn34220_write_register(vi_pipe, 0x3036, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3039, 0x2E);
    ret += mn34220_write_register(vi_pipe, 0x3041, 0x12);
    ret += mn34220_write_register(vi_pipe, 0x3058, 0x0F);
    ret += mn34220_write_register(vi_pipe, 0x306E, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x306F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3074, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3098, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3099, 0x40);
    ret += mn34220_write_register(vi_pipe, 0x309A, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3101, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3104, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3106, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3107, 0xC0);
    ret += mn34220_write_register(vi_pipe, 0x312B, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x312D, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x312F, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x3141, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3143, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3144, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3145, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3147, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3148, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3149, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x314A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x314B, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314C, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314D, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314E, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314F, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3150, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3152, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3153, 0xE3);
    ret += mn34220_write_register(vi_pipe, 0x3155, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x3157, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3159, 0x33);
    ret += mn34220_write_register(vi_pipe, 0x315B, 0x36);
    ret += mn34220_write_register(vi_pipe, 0x315D, 0x35);
    ret += mn34220_write_register(vi_pipe, 0x315F, 0x3C);
    ret += mn34220_write_register(vi_pipe, 0x3161, 0x3F);
    ret += mn34220_write_register(vi_pipe, 0x3163, 0x3A);
    ret += mn34220_write_register(vi_pipe, 0x3165, 0x39);
    ret += mn34220_write_register(vi_pipe, 0x3167, 0x28);
    ret += mn34220_write_register(vi_pipe, 0x3169, 0x2B);
    ret += mn34220_write_register(vi_pipe, 0x316B, 0x2E);
    ret += mn34220_write_register(vi_pipe, 0x316D, 0x2D);
    ret += mn34220_write_register(vi_pipe, 0x316F, 0x22);
    ret += mn34220_write_register(vi_pipe, 0x3171, 0x22);
    ret += mn34220_write_register(vi_pipe, 0x3173, 0x61);
    ret += mn34220_write_register(vi_pipe, 0x3175, 0x80);
    ret += mn34220_write_register(vi_pipe, 0x318E, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x318F, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3196, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x31FC, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x31FE, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3201, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3202, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3203, 0x35);
    ret += mn34220_write_register(vi_pipe, 0x323C, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x323E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3243, 0x75);
    ret += mn34220_write_register(vi_pipe, 0x3246, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3247, 0x3B);
    ret += mn34220_write_register(vi_pipe, 0x3248, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3249, 0xAB);
    ret += mn34220_write_register(vi_pipe, 0x324A, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x324B, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x324C, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3253, 0x7B);
    ret += mn34220_write_register(vi_pipe, 0x3256, 0x32);
    ret += mn34220_write_register(vi_pipe, 0x3258, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3259, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x325A, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x3272, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x3280, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3288, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x330E, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3310, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3315, 0x1F);
    ret += mn34220_write_register(vi_pipe, 0x331A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x331B, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3339, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x336B, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x339F, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x33A2, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x33A3, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0xD3);
    ret += mn34220_write_register(vi_pipe, 0x0100, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0101, 0x00);
    printf("===panasonic mn34220 mn34220 720P20fps 3to1 WDR(60fps->20fps) init success!=====\n");

    return;
}

void mn34220_wdr_720p_4to1_init(VI_PIPE vi_pipe)
{
    /* # NL20_S12_P2x2_HD_i2c_write 0 0x6cDRx4_V750_12b_297MHz_15fps_vM17e_150626_MCLK37_Mst_I2C_d.txt */
    /* # VCYCLE:750 HCYCLE:3300 (@MCLK) */
    HI_S32 ret = HI_SUCCESS;
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0305, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0307, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x0112, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x0113, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x3007, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x3008, 0x90);
    ret += mn34220_write_register(vi_pipe, 0x300B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3018, 0x43);
    ret += mn34220_write_register(vi_pipe, 0x3019, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x301A, 0xB9);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x53);
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0203, 0xEC);
    ret += mn34220_write_register(vi_pipe, 0x0340, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0341, 0xEE);
    ret += mn34220_write_register(vi_pipe, 0x0342, 0x22);
    ret += mn34220_write_register(vi_pipe, 0x0343, 0x60);
    ret += mn34220_write_register(vi_pipe, 0x0347, 0xF2);
    ret += mn34220_write_register(vi_pipe, 0x034A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x034B, 0xC9);
    ret += mn34220_write_register(vi_pipe, 0x034E, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x034F, 0xD8);
    ret += mn34220_write_register(vi_pipe, 0x3036, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3039, 0x2E);
    ret += mn34220_write_register(vi_pipe, 0x3041, 0x12);
    ret += mn34220_write_register(vi_pipe, 0x3058, 0x0F);
    ret += mn34220_write_register(vi_pipe, 0x306E, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x306F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3074, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3098, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3099, 0x40);
    ret += mn34220_write_register(vi_pipe, 0x309A, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3101, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3104, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3106, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3107, 0xC0);
    ret += mn34220_write_register(vi_pipe, 0x312B, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x312D, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x312F, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x3141, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3143, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3144, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3145, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3147, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3148, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3149, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x314A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x314B, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314C, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314D, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314E, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314F, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3150, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3152, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3153, 0xE3);
    ret += mn34220_write_register(vi_pipe, 0x3155, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x3157, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3159, 0x33);
    ret += mn34220_write_register(vi_pipe, 0x315B, 0x36);
    ret += mn34220_write_register(vi_pipe, 0x315D, 0x35);
    ret += mn34220_write_register(vi_pipe, 0x315F, 0x3C);
    ret += mn34220_write_register(vi_pipe, 0x3161, 0x3F);
    ret += mn34220_write_register(vi_pipe, 0x3163, 0x3A);
    ret += mn34220_write_register(vi_pipe, 0x3165, 0x39);
    ret += mn34220_write_register(vi_pipe, 0x3167, 0x28);
    ret += mn34220_write_register(vi_pipe, 0x3169, 0x2B);
    ret += mn34220_write_register(vi_pipe, 0x316B, 0x2E);
    ret += mn34220_write_register(vi_pipe, 0x316D, 0x2D);
    ret += mn34220_write_register(vi_pipe, 0x316F, 0x22);
    ret += mn34220_write_register(vi_pipe, 0x3171, 0x22);
    ret += mn34220_write_register(vi_pipe, 0x3173, 0x61);
    ret += mn34220_write_register(vi_pipe, 0x3175, 0x80);
    ret += mn34220_write_register(vi_pipe, 0x318E, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x318F, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3196, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x31FC, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x31FE, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x323C, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x323E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3243, 0x75);
    ret += mn34220_write_register(vi_pipe, 0x3246, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3247, 0x3B);
    ret += mn34220_write_register(vi_pipe, 0x3248, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3249, 0xAB);
    ret += mn34220_write_register(vi_pipe, 0x324A, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x324B, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x324C, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3253, 0x7B);
    ret += mn34220_write_register(vi_pipe, 0x3256, 0x32);
    ret += mn34220_write_register(vi_pipe, 0x3258, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3259, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x325A, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x3272, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x3280, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3288, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x330E, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3310, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3315, 0x1F);
    ret += mn34220_write_register(vi_pipe, 0x331A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x331B, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3339, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x336B, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x339F, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x33A2, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x33A3, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0xD3);
    ret += mn34220_write_register(vi_pipe, 0x0100, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0101, 0x00);
    printf("===panasonic mn34220 mn34220 720P15fps 4to1 WDR(60fps->15fps) init success!=====\n");

    return;
}

void mn34220_wdr_1080p_4to1_init(VI_PIPE vi_pipe)
{
    /* # N037_S12_P2x3_FHD_WDRx4_V1125_H200_10b_30fps_MCLK37_vE16_140401_Master.txt */
    /* # VCYCLE:1125 HCYCLE:1100 (@MCLK) */
    HI_S32 ret = HI_SUCCESS;
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0305, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0307, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x0112, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x0113, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x3004, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3008, 0x00); //  for 2ch3port
    ret += mn34220_write_register(vi_pipe, 0x300B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3018, 0x43);
    ret += mn34220_write_register(vi_pipe, 0x3019, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x301A, 0xB9);
    ret += mn34220_write_register(vi_pipe, 0x301F, 0x1F);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x53);
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0202, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x0203, 0x63);
    ret += mn34220_write_register(vi_pipe, 0x0342, 0x22);
    ret += mn34220_write_register(vi_pipe, 0x0343, 0x60);
    ret += mn34220_write_register(vi_pipe, 0x3030, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3036, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3039, 0x2E);
    ret += mn34220_write_register(vi_pipe, 0x3041, 0x12);
    ret += mn34220_write_register(vi_pipe, 0x3058, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x306E, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x306F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3074, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3098, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3099, 0x40);
    ret += mn34220_write_register(vi_pipe, 0x309A, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3101, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3104, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3106, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3107, 0x40);
    ret += mn34220_write_register(vi_pipe, 0x312B, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x312D, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x312F, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x3141, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3143, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3144, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3145, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3147, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3148, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3149, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x314A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x314B, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314C, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314D, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314E, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314F, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3150, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3152, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3153, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x3155, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x3157, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3159, 0x33);
    ret += mn34220_write_register(vi_pipe, 0x315B, 0x36);
    ret += mn34220_write_register(vi_pipe, 0x315D, 0x35);
    ret += mn34220_write_register(vi_pipe, 0x315F, 0x3C);
    ret += mn34220_write_register(vi_pipe, 0x3161, 0x3F);
    ret += mn34220_write_register(vi_pipe, 0x3163, 0x3A);
    ret += mn34220_write_register(vi_pipe, 0x3165, 0x39);
    ret += mn34220_write_register(vi_pipe, 0x3167, 0x28);
    ret += mn34220_write_register(vi_pipe, 0x3169, 0x2B);
    ret += mn34220_write_register(vi_pipe, 0x316B, 0x2E);
    ret += mn34220_write_register(vi_pipe, 0x316D, 0x2D);
    ret += mn34220_write_register(vi_pipe, 0x316F, 0x22);
    ret += mn34220_write_register(vi_pipe, 0x3171, 0x22);
    ret += mn34220_write_register(vi_pipe, 0x3173, 0x61);
    ret += mn34220_write_register(vi_pipe, 0x3175, 0x80);
    ret += mn34220_write_register(vi_pipe, 0x318E, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x318F, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3196, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x31FC, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x31FE, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x323C, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x323E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3243, 0x75);
    ret += mn34220_write_register(vi_pipe, 0x3246, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3247, 0xC9);
    ret += mn34220_write_register(vi_pipe, 0x324A, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x324B, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x324C, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3253, 0x7B);
    ret += mn34220_write_register(vi_pipe, 0x3256, 0x32);
    ret += mn34220_write_register(vi_pipe, 0x3258, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3259, 0x5C);
    ret += mn34220_write_register(vi_pipe, 0x325A, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x3272, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x3280, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3282, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x3285, 0x19);
    ret += mn34220_write_register(vi_pipe, 0x3288, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3289, 0x40);
    ret += mn34220_write_register(vi_pipe, 0x330E, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3310, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3315, 0x1F);
    ret += mn34220_write_register(vi_pipe, 0x331A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x331B, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3339, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x336B, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x339F, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x33A2, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x33A3, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0xD3);
    ret += mn34220_write_register(vi_pipe, 0x0100, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0101, 0x00);

    printf("===panasonic mn34220 mn34220 1080P30fps 4to1 WDR(120fps->30fps) init success!=====\n");

    return;
}

void mn34220_wdr_1080p_3to1_init(VI_PIPE vi_pipe)
{
    /* # N037_S12_P2x3_FHD_WDRx4_V1125_H200_10b_30fps_MCLK37_vE16_140401_Master.txt */
    /* # VCYCLE:1125 HCYCLE:1100 (@MCLK) */
    HI_S32 ret = HI_SUCCESS;
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00); // modify
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x03); // modify
    ret += mn34220_write_register(vi_pipe, 0x0112, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x0113, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x3004, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3008, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3018, 0x43); // for 2ch3port
    ret += mn34220_write_register(vi_pipe, 0x3019, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x301A, 0xB9);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x53);
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0202, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0203, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x0305, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0307, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x0340, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x0341, 0xDC);
    ret += mn34220_write_register(vi_pipe, 0x0342, 0x19);
    ret += mn34220_write_register(vi_pipe, 0x0343, 0xC8);
    ret += mn34220_write_register(vi_pipe, 0x3036, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3039, 0x2E);
    ret += mn34220_write_register(vi_pipe, 0x3041, 0x12);
    ret += mn34220_write_register(vi_pipe, 0x3058, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x306E, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x306F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3074, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3098, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3099, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x309A, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3101, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3104, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3106, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3107, 0x40);
    ret += mn34220_write_register(vi_pipe, 0x312B, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x312D, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x312F, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x3141, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3143, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3144, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3145, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3147, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3148, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3149, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x314A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x314B, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314C, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314D, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x314E, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314F, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3150, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3152, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3153, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x3155, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x3157, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3159, 0x33);
    ret += mn34220_write_register(vi_pipe, 0x315B, 0x36);
    ret += mn34220_write_register(vi_pipe, 0x315D, 0x35);
    ret += mn34220_write_register(vi_pipe, 0x315F, 0x3C);
    ret += mn34220_write_register(vi_pipe, 0x3161, 0x3F);
    ret += mn34220_write_register(vi_pipe, 0x3163, 0x3A);
    ret += mn34220_write_register(vi_pipe, 0x3165, 0x39);
    ret += mn34220_write_register(vi_pipe, 0x3167, 0x28);
    ret += mn34220_write_register(vi_pipe, 0x3169, 0x2B);
    ret += mn34220_write_register(vi_pipe, 0x316B, 0x2E);
    ret += mn34220_write_register(vi_pipe, 0x316D, 0x2D);
    ret += mn34220_write_register(vi_pipe, 0x316F, 0x22);
    ret += mn34220_write_register(vi_pipe, 0x3171, 0x22);
    ret += mn34220_write_register(vi_pipe, 0x3173, 0x61);
    ret += mn34220_write_register(vi_pipe, 0x3175, 0x80);
    ret += mn34220_write_register(vi_pipe, 0x318E, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x318F, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3196, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x31FC, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x31FE, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3201, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3202, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3203, 0x35);
    ret += mn34220_write_register(vi_pipe, 0x323C, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x323E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3243, 0x75);
    ret += mn34220_write_register(vi_pipe, 0x3246, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3247, 0xC9);
    ret += mn34220_write_register(vi_pipe, 0x324A, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x324B, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x324C, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3253, 0x7B);
    ret += mn34220_write_register(vi_pipe, 0x3256, 0x32);
    ret += mn34220_write_register(vi_pipe, 0x3258, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3259, 0x5C);
    ret += mn34220_write_register(vi_pipe, 0x325A, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x3272, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x3280, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3282, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x3285, 0x19);
    ret += mn34220_write_register(vi_pipe, 0x3288, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3289, 0x40);
    ret += mn34220_write_register(vi_pipe, 0x330E, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3310, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3315, 0x1F);
    ret += mn34220_write_register(vi_pipe, 0x331A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x331B, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3339, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x336B, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x339F, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x33A2, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x33A3, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0xD3);
    ret += mn34220_write_register(vi_pipe, 0x0100, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0101, 0x00);

    printf("===panasonic mn34220 mn34220 1080P30fps 3to1 WDR(90fps->30fps) init success!=====\n");

    return;
}

void mn34220_wdr_1080P_2to1_init(VI_PIPE vi_pipe)
{
    HI_S32 ret = HI_SUCCESS;
    ret += mn34220_write_register(vi_pipe, 0x3022, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3023, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3002, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3003, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x0304, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0305, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0306, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0307, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x0102, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0103, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0104, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0105, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0110, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0111, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0112, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x0113, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x0120, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0121, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0300, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0301, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x0302, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0303, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3004, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3005, 0x67);
    ret += mn34220_write_register(vi_pipe, 0x3006, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3007, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x3008, 0x90);
    ret += mn34220_write_register(vi_pipe, 0x3009, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x300A, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x300B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300D, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3010, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3011, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3012, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3013, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3014, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3015, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3016, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3017, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3018, 0x43);
    ret += mn34220_write_register(vi_pipe, 0x3019, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x301A, 0x39);
    ret += mn34220_write_register(vi_pipe, 0x301B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x301C, 0x2C);
    ret += mn34220_write_register(vi_pipe, 0x301D, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x301E, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x301F, 0x1F);
    ret += mn34220_write_register(vi_pipe, 0x3020, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3021, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0x53);
    ret += mn34220_write_register(vi_pipe, 0x300E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x300F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0202, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x0203, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x0204, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0205, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x020E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x020F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0210, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0211, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0212, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0213, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0214, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0215, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0220, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0221, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x033E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x033F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0340, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x0341, 0xE2);
    ret += mn34220_write_register(vi_pipe, 0x0342, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x0343, 0xA0);
    ret += mn34220_write_register(vi_pipe, 0x0344, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0345, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0346, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0347, 0x3C);
    ret += mn34220_write_register(vi_pipe, 0x0348, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0349, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x034A, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x034B, 0x7F);
    ret += mn34220_write_register(vi_pipe, 0x034C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x034D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x034E, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x034F, 0x44);
    ret += mn34220_write_register(vi_pipe, 0x0380, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0381, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0382, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0383, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0384, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0385, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0386, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0387, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0500, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0501, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0600, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0601, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0602, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0603, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0604, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0605, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0606, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0607, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0608, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0609, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x060A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x060B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x060C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x060D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x060E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x060F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0610, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x0611, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3030, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3031, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3032, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3033, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3034, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3035, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3036, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3037, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3038, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3039, 0x24);
    ret += mn34220_write_register(vi_pipe, 0x303A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x303B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x303C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x303D, 0x28);
    ret += mn34220_write_register(vi_pipe, 0x303E, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x303F, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3040, 0xC0);
    ret += mn34220_write_register(vi_pipe, 0x3041, 0x2C);
    ret += mn34220_write_register(vi_pipe, 0x3042, 0x50);
    ret += mn34220_write_register(vi_pipe, 0x3043, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3044, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3045, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3050, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3051, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3052, 0x90);
    ret += mn34220_write_register(vi_pipe, 0x3053, 0x22);
    ret += mn34220_write_register(vi_pipe, 0x3054, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3055, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3056, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3057, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3058, 0x0F);
    ret += mn34220_write_register(vi_pipe, 0x3059, 0xFE);
    ret += mn34220_write_register(vi_pipe, 0x305A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x305B, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x305C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x305D, 0x31);
    ret += mn34220_write_register(vi_pipe, 0x305E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x305F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3060, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3061, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3062, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x3063, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x3064, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3065, 0x32);
    ret += mn34220_write_register(vi_pipe, 0x3066, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3067, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3068, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3069, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x306A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x306B, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x306C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x306D, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x306E, 0x3F);
    ret += mn34220_write_register(vi_pipe, 0x306F, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3070, 0x3F);
    ret += mn34220_write_register(vi_pipe, 0x3071, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3072, 0x3F);
    ret += mn34220_write_register(vi_pipe, 0x3073, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3074, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3075, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3076, 0x42);
    ret += mn34220_write_register(vi_pipe, 0x3077, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3078, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3079, 0x13);
    ret += mn34220_write_register(vi_pipe, 0x307A, 0x12);
    ret += mn34220_write_register(vi_pipe, 0x307B, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x307C, 0x2B);
    ret += mn34220_write_register(vi_pipe, 0x307D, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x307E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x307F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3080, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3081, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3082, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3083, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3084, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3085, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3086, 0x23);
    ret += mn34220_write_register(vi_pipe, 0x3087, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3088, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x3089, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x308A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x308B, 0x0B);
    ret += mn34220_write_register(vi_pipe, 0x308C, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x308D, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x308E, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x308F, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x3090, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3091, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3092, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3093, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x3094, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3095, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3096, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3097, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3098, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3099, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x309A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x309B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x309C, 0x53);
    ret += mn34220_write_register(vi_pipe, 0x309D, 0x54);
    ret += mn34220_write_register(vi_pipe, 0x309E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x309F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3100, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3101, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3102, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3103, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3104, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3105, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3106, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3107, 0xC0);
    ret += mn34220_write_register(vi_pipe, 0x3108, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3109, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x310A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x310B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x310C, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x310D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x310E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x310F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3110, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3111, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3112, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3113, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3114, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3115, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3116, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3117, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3118, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3119, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x311A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x311B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x311C, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x311D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x311E, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x311F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3120, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3121, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3122, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3123, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3124, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3125, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3126, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3127, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3128, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3129, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312B, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x312C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312D, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x312E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x312F, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x3130, 0x0F);
    ret += mn34220_write_register(vi_pipe, 0x3131, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3132, 0x67);
    ret += mn34220_write_register(vi_pipe, 0x3133, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3134, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3135, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3136, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3137, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3138, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3139, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x313A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x313B, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x313C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x313D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3140, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3141, 0x40);
    ret += mn34220_write_register(vi_pipe, 0x3142, 0x50);
    ret += mn34220_write_register(vi_pipe, 0x3143, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3144, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3145, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3146, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3147, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3148, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3149, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x314A, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x314B, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x314C, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x314D, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x314E, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x314F, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3150, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x3151, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3152, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3153, 0xF1);
    ret += mn34220_write_register(vi_pipe, 0x3154, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3155, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3156, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3157, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3158, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3159, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x315A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x315B, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x315C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x315D, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x315E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x315F, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3160, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3161, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3162, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3163, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3164, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3165, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3166, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3167, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3168, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3169, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x316A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x316B, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x316C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x316D, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x316E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x316F, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3170, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3171, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3172, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3173, 0xCA);
    ret += mn34220_write_register(vi_pipe, 0x3174, 0x0B);
    ret += mn34220_write_register(vi_pipe, 0x3175, 0x80);
    ret += mn34220_write_register(vi_pipe, 0x3176, 0x88);
    ret += mn34220_write_register(vi_pipe, 0x3177, 0xA0);
    ret += mn34220_write_register(vi_pipe, 0x3178, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3179, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x317A, 0xA0);
    ret += mn34220_write_register(vi_pipe, 0x317B, 0xA2);
    ret += mn34220_write_register(vi_pipe, 0x317C, 0xA0);
    ret += mn34220_write_register(vi_pipe, 0x317D, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x317E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x317F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3180, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3181, 0x82);
    ret += mn34220_write_register(vi_pipe, 0x3182, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x3183, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x3184, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3185, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3186, 0x48);
    ret += mn34220_write_register(vi_pipe, 0x3187, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3188, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3189, 0xDE);
    ret += mn34220_write_register(vi_pipe, 0x318A, 0x6B);
    ret += mn34220_write_register(vi_pipe, 0x318B, 0x0F);
    ret += mn34220_write_register(vi_pipe, 0x318C, 0x1F);
    ret += mn34220_write_register(vi_pipe, 0x318D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x318E, 0x20);
    ret += mn34220_write_register(vi_pipe, 0x318F, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x3190, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3191, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3192, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3193, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3194, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3195, 0x40);
    ret += mn34220_write_register(vi_pipe, 0x3196, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3197, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3198, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3199, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x319A, 0x0E);
    ret += mn34220_write_register(vi_pipe, 0x319B, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x319C, 0x32);
    ret += mn34220_write_register(vi_pipe, 0x319D, 0x54);
    ret += mn34220_write_register(vi_pipe, 0x319E, 0x76);
    ret += mn34220_write_register(vi_pipe, 0x319F, 0x98);
    ret += mn34220_write_register(vi_pipe, 0x31A0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31A1, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31A2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31A3, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x31A4, 0x32);
    ret += mn34220_write_register(vi_pipe, 0x31A5, 0x54);
    ret += mn34220_write_register(vi_pipe, 0x31A6, 0x86);
    ret += mn34220_write_register(vi_pipe, 0x31A7, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x31A8, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31A9, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31AA, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31AB, 0x24);
    ret += mn34220_write_register(vi_pipe, 0x31AC, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31AD, 0x89);
    ret += mn34220_write_register(vi_pipe, 0x31AE, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x31AF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B1, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B3, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B5, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B6, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B7, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B8, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31B9, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31BA, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31BB, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31BC, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31BD, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31BE, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31BF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C1, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C3, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C5, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C6, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C7, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C8, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31C9, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31CA, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31CB, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31CC, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31CD, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31CE, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31CF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D1, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D3, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D5, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D6, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D7, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D8, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31D9, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31DA, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31DB, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31DC, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31DD, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31DE, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31DF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E1, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E3, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E5, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E6, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E7, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E8, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31E9, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31EA, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31EB, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31EC, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31ED, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31EE, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31EF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F1, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F3, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F5, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F6, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x31F7, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x31F8, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x31F9, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x31FA, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x31FB, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x31FC, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x31FD, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x31FE, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x31FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3200, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3201, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3202, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3203, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3204, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3205, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3206, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3207, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3208, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3209, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x320A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x320B, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x320C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x320D, 0x1A);
    ret += mn34220_write_register(vi_pipe, 0x320E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x320F, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x3210, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3211, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x3212, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3213, 0x0B);
    ret += mn34220_write_register(vi_pipe, 0x3214, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3215, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3216, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3217, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3218, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3219, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x321A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x321B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x321C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x321D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x321E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x321F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3220, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3221, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3222, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3223, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3224, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3225, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3226, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3227, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3228, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3229, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x322A, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x322B, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x322C, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x322D, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x322E, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x322F, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3230, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3231, 0xFF);
    ret += mn34220_write_register(vi_pipe, 0x3232, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3233, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3234, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3235, 0xBA);
    ret += mn34220_write_register(vi_pipe, 0x3236, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3237, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3238, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3239, 0xBA);
    ret += mn34220_write_register(vi_pipe, 0x323A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x323B, 0x81);
    ret += mn34220_write_register(vi_pipe, 0x323C, 0x70);
    ret += mn34220_write_register(vi_pipe, 0x323D, 0x80);
    ret += mn34220_write_register(vi_pipe, 0x323E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x323F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3240, 0x15);
    ret += mn34220_write_register(vi_pipe, 0x3241, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x3242, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3243, 0xD1);
    ret += mn34220_write_register(vi_pipe, 0x3244, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3245, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x3246, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3247, 0xA0);
    ret += mn34220_write_register(vi_pipe, 0x3248, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3249, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x324A, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x324B, 0x34);
    ret += mn34220_write_register(vi_pipe, 0x324C, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x324D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x324E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x324F, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x3250, 0x31);
    ret += mn34220_write_register(vi_pipe, 0x3251, 0x0E);
    ret += mn34220_write_register(vi_pipe, 0x3252, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3253, 0xD4);
    ret += mn34220_write_register(vi_pipe, 0x3254, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3255, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3256, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x3257, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3258, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3259, 0x90);
    ret += mn34220_write_register(vi_pipe, 0x325A, 0x39);
    ret += mn34220_write_register(vi_pipe, 0x325B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x325C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x325D, 0x0C);
    ret += mn34220_write_register(vi_pipe, 0x325E, 0x84);
    ret += mn34220_write_register(vi_pipe, 0x325F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3260, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3261, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3270, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3271, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3272, 0x55);
    ret += mn34220_write_register(vi_pipe, 0x3273, 0xAB);
    ret += mn34220_write_register(vi_pipe, 0x3274, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3275, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x3280, 0x30);
    ret += mn34220_write_register(vi_pipe, 0x3281, 0x10);
    ret += mn34220_write_register(vi_pipe, 0x3282, 0x0E);
    ret += mn34220_write_register(vi_pipe, 0x3283, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3284, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3285, 0x1B);
    ret += mn34220_write_register(vi_pipe, 0x3286, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x3287, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3288, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3289, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x328A, 0xE8);
    ret += mn34220_write_register(vi_pipe, 0x328B, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x328C, 0x75);
    ret += mn34220_write_register(vi_pipe, 0x328D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3300, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3301, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3302, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3303, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x3304, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3305, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x3306, 0x19);
    ret += mn34220_write_register(vi_pipe, 0x3307, 0x19);
    ret += mn34220_write_register(vi_pipe, 0x3308, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3309, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x330A, 0x1E);
    ret += mn34220_write_register(vi_pipe, 0x330B, 0x1E);
    ret += mn34220_write_register(vi_pipe, 0x330C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x330D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x330E, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x330F, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x3310, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3311, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3312, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3313, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3314, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3315, 0x19);
    ret += mn34220_write_register(vi_pipe, 0x3316, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x3317, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3318, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3319, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x331A, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x331B, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x331C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x331D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x331E, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x331F, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3320, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3321, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3322, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3323, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3324, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3325, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3326, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x3327, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3328, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3329, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x332A, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x332B, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x332C, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x332D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x332E, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x332F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3330, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3331, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3332, 0x12);
    ret += mn34220_write_register(vi_pipe, 0x3333, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3334, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3335, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3336, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3337, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3338, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3339, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x333A, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x333B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x333C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x333D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x333E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x333F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3340, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3341, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3342, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3343, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3344, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3345, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3346, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3347, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3348, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x3349, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x334A, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x334B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x334C, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x334D, 0x1C);
    ret += mn34220_write_register(vi_pipe, 0x334E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x334F, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3350, 0x0E);
    ret += mn34220_write_register(vi_pipe, 0x3351, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3352, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3353, 0x05);
    ret += mn34220_write_register(vi_pipe, 0x3354, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x3355, 0x19);
    ret += mn34220_write_register(vi_pipe, 0x3356, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3357, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x3358, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x3359, 0x0B);
    ret += mn34220_write_register(vi_pipe, 0x335A, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x335B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x335C, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x335D, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x335E, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x335F, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3360, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x3361, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x3362, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x3363, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3364, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3365, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3366, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x3367, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3368, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x3369, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x336A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x336B, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x336C, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x336D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x336E, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x336F, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3370, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3371, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3372, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3373, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3374, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3375, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3376, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3377, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3378, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x3379, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x337A, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x337B, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x337C, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x337D, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x337E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x337F, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3380, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3381, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3382, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3383, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3384, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x3385, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3386, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3387, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3388, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x3389, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x338A, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x338B, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x338C, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x338D, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x338E, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x338F, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x3390, 0x02);
    ret += mn34220_write_register(vi_pipe, 0x3391, 0x0F);
    ret += mn34220_write_register(vi_pipe, 0x3392, 0x04);
    ret += mn34220_write_register(vi_pipe, 0x3393, 0x09);
    ret += mn34220_write_register(vi_pipe, 0x3394, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x3395, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x3396, 0x07);
    ret += mn34220_write_register(vi_pipe, 0x3397, 0x18);
    ret += mn34220_write_register(vi_pipe, 0x3398, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3399, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x339A, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x339B, 0x08);
    ret += mn34220_write_register(vi_pipe, 0x339C, 0x0D);
    ret += mn34220_write_register(vi_pipe, 0x339D, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x339E, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x339F, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x33A0, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33A1, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x33A2, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x33A3, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x33A4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33A5, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x33A6, 0x06);
    ret += mn34220_write_register(vi_pipe, 0x33A7, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33A8, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33A9, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33AA, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33AB, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33AC, 0x03);
    ret += mn34220_write_register(vi_pipe, 0x33AD, 0x14);
    ret += mn34220_write_register(vi_pipe, 0x33AE, 0x3F);
    ret += mn34220_write_register(vi_pipe, 0x33AF, 0x11);
    ret += mn34220_write_register(vi_pipe, 0x33B0, 0x0A);
    ret += mn34220_write_register(vi_pipe, 0x33B1, 0x1A);
    ret += mn34220_write_register(vi_pipe, 0x33B2, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33B3, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33B4, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x33B5, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x00FF, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3000, 0x00);
    ret += mn34220_write_register(vi_pipe, 0x3001, 0xD3);
    ret += mn34220_write_register(vi_pipe, 0x0100, 0x01);
    ret += mn34220_write_register(vi_pipe, 0x0101, 0x00);

    printf ("===panasonic mn34220 sensor 1080P30fps 2to1 WDR(30fps)(MIPI port) init success!=====\n");
    return;
}
